WATT AI is developing next-gen AI processors and computing clusters.
Headquarter in Singapore, it is co-founded by hardware and software industry experts from Silicon Valley.
Why WATT AI?
Our Mission
Our Services
Our Services
The fastest and most flexible infrastructure for high-performance computing.
Our Services
Our Services
Our Services
A cloud solutions provider that encourages scale instead of inhibiting it.
Our Team
Our Services
Our Team
Industry’s best economics. Period.
Offering best-in-class support for your team.
We're Hiring now!
Join Our Team
WATT AI PTE LTD (www.wattai.tech) is an innovative high-tech company co-founded by hardware and software experts working on next-gen AI processors and models from Silicon Valley. It is committed to developing high-performance AI chips and computing clusters that support ultra-large-scale AI model training. Create a complete software and hardware integration solution, provide global customers with AI innovation technology solutions with capabilities to produce and evolve, and accelerate the process of AI implementation and industrialization.
We are looking to grow our team in Singapore with the most intelligent people of the world. Together, we can really make a change. If you're interested in one of our open positions, start by applying here and attaching your resume.
1. Back-End IC Engineer (3-4 openings)
As a Back-End IC Engineer, you will apply the latest design methodology and milestone flow to deliver state-of-the-art design over advanced technology node from RTL to GDSII. You should have very good experience in layout activities of block and level, including floor-
planning, partitioning, placement, clock tree synthesis, route and physical verification.
Responsibilities
1. Understanding of SoC for top-down/bottom-up physical design integration in advanced technologies.
2. Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows.
3. Must have knowledge of P&R, Extraction, Physical Verification, STA, ECO.
4. Build automation flows wherever needed/adapt to existing flows for re-use.
Key Qualifications
1. A Master’s Degree in EE, CS, Math, Physics or related subjects, PhD preferred.
2. A deep understanding of backend digital design flow.
3. Proficient in timing constraints, physical constraints.
4. Proficient in handling EDA tools across floorplan/partition/placement/CTS/route stages for SoC top-level.
5. Proficient with backend EDA tools Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PrimeTime, PrimeRail/Voltus, Redhawk
Preferred Qualifications
1. Proficiency in scripting languages (e.g., Tcl, Perl)
2. DFT Engineer (3-4 openings)
As a DFT Engineer, your role is about embedding testability features directly into the design phase of these intricate circuits, thereby facilitating streamlined testing procedures, early fault detection, and expedited fault diagnosis during manufacturing. By incorporating DFT principles, engineers significantly mitigate risks associated with defects, accelerate time-to-market, and uphold stringent quality standards, thus fortifying the foundation upon which the semiconductor industry continues to innovate and thrive.
Responsibilities
1. Test Structure Integration: DFT engineers work on integrating specific test structures and logic directly into the chip’s architecture. This integration involves strategically placing components within the design that allow for comprehensive testing. They create and embed features such as scan chains, Built-In Self-Test (BIST) modules, and other test access mechanisms that enable thorough testing of the chip’s functionality.
2. Test Methodologies Development: These engineers are responsible for developing innovative and efficient test methodologies. They design algorithms and strategies aimed at detecting potential faults or defects within semiconductor devices. This involves creating complex testing scenarios and protocols to thoroughly evaluate different functionalities and potential failure points of the chip.
3. Compliance with Standards: DFT engineers ensure that the testability features implemented in semiconductor designs comply with industry standards and protocols. They stay updated with the latest standards and guidelines to ensure compatibility across diverse manufacturing and testing platforms. By adhering to these standards, they enable easier interoperability and compatibility between different chips and testing equipment.
4. Collaboration with Design Teams: DFT engineers collaborate closely with various teams, including design, verification, and manufacturing, to ensure that the testability features are seamlessly integrated into the chip design without compromising its performance or functionality. Their work significantly contributes to the overall quality, reliability, and manufacturability of semiconductor products in the market.
5. Debugging and Troubleshooting: In the event of test failures or issues during manufacturing, DFT engineers troubleshoot problems, analyze test results, and identify the root causes of failures. They work on solutions to rectify these issues and ensure the integrity of the circuits.
Key Qualifications
1. A Master’s Degree in EE, CS, Math, Physics or related subjects, PhD preferred.
2. Proficiency in digital design and verification methodologies, demonstrates an adept command of digital design principles, navigating the intricacies of RTL coding and simulation.
3. In-depth knowledge of DFT architectures and methodologies, including scan, Built-In Self-Test (BIST), and the intricate intricacies of Design for Debug (DFD).
4. Familiarity with Automatic Test Pattern Generation (ATPG) tools and fault models to generate efficient test patterns for manufacturing tests.
Preferred Qualifications
1. Expertise in scripting languages (e.g., Perl, Python).
2. Strong understanding of industry-standard test protocols and standards (e.g., IEEE 1149.1, IEEE 1500).
3. AI Architect (3-4 openings)
As an AI Architect, you will be contributing towards the architectural development, specification, modelling and evaluation of our AI processor. You will closely interact with both hardware and software teams, be fluent in their languages and work efficiently with them to evaluate and debug existing hardware as well as facilitate the design and implementation of future products, driving the continuous innovation of our company.
Responsibilities
1. Specification and modelling of current and future revisions of the architecture of our product.
2. Contributing to the micro-architectural development, including but not limited to core, on-chip network, inter-chip connects, etc.
3. Working with the hardware and software teams to ensure correct and consistent design implementation.
Key Qualifications
1. A Master’s Degree in EE, CS, Math, Physics or related subjects, PhD preferred.
2. Solid understanding in architecture of CPU, GPU, and similar accelerators.
3. Experience in modeling and evaluation using software toolchain flows.
Preferred Qualifications
1. Knowledge of massively parallel computing systems.
2. Experience in high-level programming languages and assembly.
3. Experience in performance benchmarking.
4. Knowledge in IC design and verification methodology.
5. Experience in silicon bring-up and debug.
Responsible Employer, Sustainable Business
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